The present invention generally relates to a method of annealing deeply buried metallic interconnects, such as through silicon vias (TSVs) and other metallic interconnects of an integrated circuit (IC).
Three dimensional (3D) integrated circuits are prepared by stacking wafers and/or dies and interconnecting them using a vertical electrical connection (via), such as a TSV, or other deeply buried metallic interconnect. TSV extends through the entire thickness of a finished substrate to make electrical connections between stacked wafers or dies. Accordingly, TSV is a metallic interconnect deeply buried within substrate.
TSV and other buried metallic interconnects are most commonly made from copper to reduce their electrical resistivity. After copper deposition, TSV fabrication often includes annealing steps that may grow the copper grain size, may alter stress in the metal, and may induce a plastic deformation of the metal. Current methods for annealing TSVs use a mild heat exposure, typical for forming copper interconnects, with highest temperature not exceeding 400° C. (e.g. 375° C.) for an extended period of time (e.g. about 2 and up to 6 hours). Extended annealing makes the temperature uniform throughout substrate thickness leading to an isothermal annealing of any deeply buried interconnects. Annealing at these temperatures for an extended time period results in copper grain growth along the full length and width of the TSV, which in some instances can reach up to about 55 micrometers into the substrate and can be of large diameter (upward of 6 to 19 micrometers). A post TSV anneal may be of substantially high temperature (e.g. 375° C.) for a long duration to ensure that subsequent exposure of the TSV to any thermal heating during further processing steps of IC fabrication do not result in further grain growth and upward expansion of the metal, which can cause cracking of wiring levels/dielectric films above the TSVs. A problem with such additional post TSV annealing for an extended time period is that it adds to the overall device thermal budget beyond what 2D structures experience and may lead to the plastic deformation of metal. Furthermore, the long anneals add significant processing time for 3D device fabrication, making the process costly.
Millisecond scale annealing of metallic interconnects can be conducted at a much higher temperature, up to the melting point of metal (e.g. copper at 1085° C.) without detrimental effects associated with longer anneals at lower temperatures. It has been shown that such high-temperature millisecond-scale annealing results in substantial copper grain growth. However, millisecond scale annealing confines the region of high temperature annealing to within the proximity of wafer surfaces creating obstacles to uniform annealing of deep, buried metallic interconnects.